Authors: Paolo Ienne, Rainer Leupers
ISBN-13: 9780123695260, ISBN-10: 0123695260
Format: Hardcover
Publisher: Elsevier Science
Date Published: July 2006
Edition: (Non-applicable)
Customizable processors have been described as the next natural step in the evolution of the microprocessor business: a step in the life of a new technology where top performance alone is no longer sufficient to guarantee market success. Other factors become fundamental, such as time to market, convenience, energy efficiency, and ease of customization.
This book is the first to explore comprehensively one of the most fundamental trends which emerged in the last decade: to treat processors not as rigid, fixed entities, which designers include “as is” in their products; but rather, to build sound methodologies to tailor-fit processors to the specific needs of such products. This book addresses the goal of maintaining a very large family of processors, with a wide range of features, at a cost comparable to that of maintaining a single processor.
· First book to present comprehensively the major ASIP design methodologies and tools without any particular bias.
· Written by most of the pioneers and top international experts of this young domain.
· Unique mix of management perspective, technical detail, research outlook, and practical implementation.
In praise of customizable embedded processors | ||
1 | From pret-a-porter to tailor-made | 3 |
2 | Opportunities for application-specific processors : the case of wireless communications | 11 |
3 | Customizing processors : lofty ambitions, stark realities | 39 |
4 | Architecture description languages | 59 |
5 | C compiler retargeting | 77 |
6 | Automated processor configuration and instruction extension | 117 |
7 | Automatic instruction-set extensions | 145 |
8 | Challenges to automatic customization | 185 |
9 | Coprocessor generation from executable code | 209 |
10 | Datapath synthesis | 233 |
11 | Instruction matching and modeling | 257 |
12 | Processor verification | 281 |
13 | Sub-RISC processors | 303 |
14 | Application specific instruction set processor for UMTS-FDD cell search | 339 |
15 | Hardware/software tradeoffs for advanced 3G channel decoding | 361 |
16 | Application code profiling and ISA synthesis on MIPS32 | 381 |
17 | Designing soft processors for FPGAs | 425 |